Packaging is the bridge connecting the chip and the external circuit, and the impact of packaging technology on the performance of the chip is mainly reflected in several aspects:
Improving system performance: As Moore's Law iterations slow down, advanced packaging technology has become another major development axis to improve system performance. With integrated packaging, chip performance can be improved simply by improving the packaging without shrinking the process node.
Improve signal transmission efficiency and stability: Packaging technology can protect the chip from environmental factors, while improving signal transmission efficiency and stability, which is essential for the stable performance of the chip.
Enhanced chip performance: Packaging technology meets the demands of the increasing complexity of modern electronic devices by increasing integration. On the one hand, increase the functional density of a single chip; On the other hand, through technologies such as system-in-package (SiP), multiple chips with different functions are integrated together to form a complete system, thereby enhancing chip performance.
Reduced signal transmission delay: High-performance packaging process developments include improving the electrical performance of the chip, such as reducing signal transmission delay and improving signal integrity. By employing advanced packaging technologies such as Flip-Chip technology and Ball Grid Array Package (BGA) technology, shorter electrical connection paths can be achieved, thereby reducing latency and loss during signal transmission.
Improved heat dissipation: As chips become more integrated and performant, chips generate more and more heat. New packaging technologies focus on improving heat dissipation, such as using packaging materials with better heat dissipation performance, optimizing the package structure to increase heat dissipation paths, etc., which are essential to maintain chip performance and reliability.
Three-dimensional packaging (3D packaging): Three-dimensional packaging technology can achieve higher integration and performance in a limited space by stacking different chip layers, which is of great significance for improving chip performance and enabling more complex functions.
Protect the chip from damage: The packaging material protects the chip from external factors such as particles, moisture, and mechanical forces, while also enhancing heat dissipation.
With the development of technology, the diverse application needs have created a series of packaging media and packaging processes.
Here are some common power IC package types:
TO packages: including TO-220 and TO-247, these are discrete packages that are widely used in the small power range and need to be soldered to a printed circuit board. Due to the relatively low power losses and low thermal requirements, this package design typically does not feature internal insulation, with only one switch in each package.
Module stackup structure: including TO-247 single-tube package and module package, the shell, chip, terminal and bond wire are the main components.
Flip SMD Packaging: Drawing on BGA's packaging technology, the University of Arkansas team proposed a single-tube flip chip packaging technology that can effectively reduce the stray inductance value and control its size below 5nH.
DBC+PCB Hybrid Packaging: This packaging method combines the advantages of two mature processes, is easy to fabricate, and can achieve low stray inductance and smaller size.
SKiN package: The 1200V/400A SiC module made by Semikron using SKiN packaging technology uses a flexible PCB board instead of a bonding wire to realize the electrical connection of the upper and lower surfaces of the chip, and the parasitic inductance of the internal loop of the module is only 1.5nH.
DLB, Cu-Clip, and SiPLIT Packages: These packaging technologies enable front-of-chip connectivity through planar interconnects, reducing current loops, resulting in stray inductance and resistance, and improved temperature cycling characteristics and reliability.
In different fields, different products have their own characteristics, for example, a few of the most commonly used packaging specifications in power ICs
TO-220/220F: This is a discrete package that is widely used in the small power range. TO-220F is an all-plastic package, and there is no need to add an insulating pad when installed on the radiator; The TO-220 is connected to the middle foot with a metal sheet, and an insulating pad should be added when installing the radiator.
TO-251: This package is mainly used in environments with medium voltage and high current of 60 A or less and high voltage of 7 A or less in order to reduce cost and product size.
TO-92: This package is only used for low-voltage MOS transistors (current 10A or less, withstand voltage value of 60V or less) and high-voltage 1N60/65 in order to reduce costs.
TO-252 (D-PAK): This is a plastic chip package, which is commonly used in the packaging of power transistors and voltage regulator chips, and is one of the mainstream packages. MOSFETs in this package have three electrodes: gate (G), drain (D), and source (S). Among them, the pin of the drain (D) is not cut, but the heat sink on the back is used as the drain (D), which is directly soldered on the PCB, which is used to output large current on the one hand, and dissipate heat through the PCB on the other hand.
TO-263 (D2PAK): This is a variant of TO-220, which is mainly designed to improve production efficiency and heat dissipation, and supports extremely high currents and voltages, which are more common in medium-voltage and high-current MOS tubes below 150A and above 30V.
